Many types of semiconductor memories, including static random access memories (SRAMs), dynamic random access memories (DRAMs), FIFOs, dual-port memories, and read-only memories of various types, fabricated as individual components and embedded in other integrated circuits such as microprocessors and other logic devices, are containing greater numbers of storage locations, and higher capacity, as the manufacturing technology improves. For example, SRAMs having 2.sup.20 storage locations (i.e., 1 Mbits) and DRAMs having 2.sup.22 storage locations (i.e., 4 Mbits) are available in the market.
For the general commercial market, such a memory is usable only if each and every storage location can be accessed and can store both digital data states. Failure of a single storage location, or bit, thus causes the entire memory (and logic device having an embedded memory) to be non-salable. Considering the relatively large chip size and high manufacturing costs for the high density memories noted hereinabove, such memories are particularly vulnerable to the effect of extremely small (in some cases sub-micron) defects that cause single "stuck" bits.
As a result, many semiconductor memories are now fabricated with so-called redundant storage locations, which are enabled in the event of defects in the primary memory array. For ease of enabling, and also to address row or column defects, the redundant storage locations are generally formed as redundant rows or columns which, when enabled, replace an entire row or column of the primary memory array. The enabling of such redundant storage location is conventionally done during the manufacturing test process, where the primary memory is tested for functionality of the bits therein. The addresses of failing bits are logged, and an algorithm in the automated test equipment determines if the redundant rows or columns available on the circuit are sufficient to replace all of the failing bits. If so, fuses are opened (or, alternatively, anti-fuses may be closed) in the decoding circuitry of the memory so that the failing row or column is no longer enabled by its associated address value, and so that a redundant row or column is enabled by the address associated with the failing row or column. Examples of memory devices incorporating conventional redundancy schemes are described in Hardee, et al., "A Fault-Tolerant 30 ns/375 mW 16K.times.1 NMOS Static RAM", J. Solid State Circuits, Vol. SC-16, No. 5 (IEEE, 1981), pp. 435-43, and in Childs, et al., "An 18 ns 4K.times.4 CMOS SRAM", J. Solid State Circuits, Vol. SC-19, No. 5 (IEEE, 1984), pp. 545-51.
Especially for high-performance memories, two competing constraints must be dealt with in the design of such redundant storage locations. A first of these constraints is the access time of the redundant storage locations relative to the access time of bits in the primary array. Access of the redundant elements is typically slower than access of the bits in the primary array (or, at least, slower than the access time of bits in a similar not utilizing redundancy). The reduction in performance is generally due to either additional logic circuitry for selecting the redundant rows or columns or to increased internal signal loading due to the redundancy.
A second constraint in the design of a memory with redundancy is the chip area required to incorporate the redundant elements and associated decode circuitry. The choice of the number of redundant rows and columns generally depends on an estimate of the types of defects which will be encountered in the manufacture of the memories, with the designer required to make a trade-off between the additional chip area required for redundancy and the expected number of otherwise failing circuits which can be repaired by redundancy.
For memories with multiple inputs and outputs, the organization of the redundant rows and columns (particularly columns) further complicates the design, as either selection circuitry must be provided to allow a redundant column, for example, to communicate with each of the multiple inputs and outputs, or additional redundant columns must be provided (over the number which would be necessary in a single input/output memory) with each dedicated to a particular input/output. While the use of selection circuitry reduces the number of redundant columns necessary in a multiple input/output memory, the selection circuitry in the read and write paths to and from the redundant storage locations will slow the access time of the redundant memory cells.
It is therefore an object of this invention to provide a redundancy scheme which allows for efficient repairability without significant decrease in the performance of accesses to the redundant storage locations.
It is another object of this invention to provide such a scheme which is particularly adaptable to multiple input/output memories.
It is another object of this invention to provide such a scheme which is particularly adaptable to redundant columns.
Further objects and advantages of the invention will be apparent to those of ordinary skill in the art having reference to this specification.